As geometric transistor scaling becomes more difficult and less effective in providing adequate performance enhancements, there is an incentive to improve the performance of transistors by enhancing innate carrier mobility by, e.g., application of strain to the semiconductor channel material. Although process simplicity is maintained by the application of one type of strain (or one type of channel material) for both NMOS and PMOS devices, overall performance would be greatly improved if it were possible to enhance the performance of each type of device separately. Traditionally, this enhancement has been incomplete—one type of channel material is typically used for both device types, with selective application of strain to the channel material for each device.
Devices are advantageously formed on semiconductor-on-insulator (SOI) substrates. Such substrates offer the benefits of an insulating substrate, such as reduced parasitic capacitances and improved isolation.